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Super FinSim v9.1.12 LINUX64 英文正式版(附帶OVI的Virology編譯器軟體)

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Super FinSim v9.1.12 LINUX64 英文正式版(附帶OVI的Virology編譯器軟體)

商品名稱: Super FinSim v9.1.12 LINUX64

商品分類: Linux系統專用軟體

商品類型: 附帶OVI的Virology編譯器軟體

語系版本: 英文正式版

運行平台: LINUX (以官方網站為準)

更新日期: 2007-07-12

熱門標籤: 附帶OVI的Virology編譯器軟體 FinSim Super


破解說明:

Install instruction
-------------------
1. Install application, make sure to toggle the NO DONGLE option.
2. copy our supplied license.dat from /CRACK to program dir(ie ...\FinSim\bin\cl)
3. You MUST add the full path to the LM_LICENSE_FILE environment variable AND
create FINTRON_LICENSE_FILE environment variable also with full path to license file(ie ...\FinSim\bin\cl),
also same with FINTRONIC env. variable. all three must contain full path including license.dat filename!
Voila! Enjoy another fine release from Team LineZer0
內容說明:

Super-FinSim 仿真環境由一個附帶OVI的Virology編譯器,一個仿真構件和一個仿真內
核組成。Verilog編譯器用於(1)檢查設計的句法和語意的正確性, (2)依據設計要
求產生配置仿真內核所要求的代碼和數據。 (3)選擇性的產生一個供其它應用程式
理的中間格式表達。仿真構件用於鏈接構成一個仿真器所需要的所有文件,例如,編譯
器的輸出和仿真內核。主C鏈接器用於此目的。 仿真內核是所有Veilog設計仿真公共代
碼。一旦配置完成,仿真內核就成為一個定制的Verilog設計的仿真器。Super-FinSim
的仿真器可以運行
Super-FinSim Verilog 編譯器有一個快速和強大的能進行廣泛錯誤檢查和恢復的分析
器。此外,分析器能產生標明潛在設計錯誤的警告資訊代碼,例如,交換一個越界的數
組元素。
Super-FinSim Verilog 編譯器支援來自Verilog-XL的一些編譯器選項, 包括控制庫搜
索功能的選項。為便於引用命令文件同樣得到支援。必需事先指定希望的Super-FinSim
仿真器模式,不管是編譯,解釋或編譯、解釋的混合狀態。如果不指定,Super-FinSim
將會試圖仿真編譯模式下的整個設計,如果發現了一個許可的編譯仿真器,否則,將在
解釋模式仿真設計。所有的編譯資訊儲存在登記文件『finvc.log』。
Super-FinSim仿真器使用仿真內核的波形例程介面支援實時波形顯示。最近的
Super-FinSim從數據I/O的工程捕捉系統(ECS)和 Veribest』s Veriscope支援實時波
形顯示。用ECS波形顯示構造仿真器,必須指定選項『-ecs』。用Veriscope波形顯示構
造仿真器,必須指定選項 『-veriscope』。
英文說明:

Fintronic USA Inc. is a provider of high performance
Electronic Design Automation (EDA) tools. These tools are
crucial for the design of digital circuits. The first step
in the design of a digital circuit is to formally describe
the desired functionality of the circuit in a Hardware
Design Language, such as Verilog HDL. This description of
the circuit is used as input to a simulator which will
enable the designer to find out whether the described
circuit is indeed what is needed. If not, the specification
(in the form of the Verilog description) is modified until
it becomes acceptable. Once satisfied with the
functionality, the designer refines and details this
description to lower levels of abstraction (the "register
transfer level" and the "gate level"), with the ultimate
goal of creating a very simple description of the circuit
which can then be sent to the fabrication facilities where
the actual silicon chips are produced. During this process
of refining the description of the design, the design
engineer has to continue to simulate the circuit to ensure
that the original functionality is still maintained.

Given the increased complexity of modern day chips and the
critical importance of market timing, the electronics
industry is craving for increased verification throughput
which can reduce the turnaround time of the design cycles.
Fintronic USA addresses these issues by providing Super
FinSim, which is one of the most accurate and fast Verilog
simulators in the industry. The simulation speed is achieved
by using a mixed compiled and interpreted event driven
simulator in conjunction with the Enhanced Cycle Simulation
Technology. The main gain in throughput is achieved by using
FinFarm, the simulation farm management tool. Super FinSim
is especially fit for being used in a simulation farm
because it uses little memory and the results it produces
are compact when compared with the competitionn.

Along with its Verilog simulators Fintronic USA provides
other related EDA tools which help the design engineer
during the design cycle such as support for FinMath, a
superset of Verilog that supports mathematical descriptions,
and FinCov, a code coverage tool that provides the user with
feedback regarding the quality of the test vectors used to
verify the digital circuit, by reporting how many times each
line is executed. Another extremely useful tool is FinVA
which allows users to syntactically and semantically verify
a Verilog description and create an attributed intermediate
format which can be used in conjunction with the FinVFI
package to create any tool for Verilog
analysis/synthesis/verification.

Super-FinSim is Fintronic's top performance, fully compliant
Verilog simulator. It supports PLI 1.0, SDF, VCD, SystemC,
FinMath and provides through integration with third party
source level debuggers, waveform displays etc. a complete
simulation environment on all popular platforms. FinSim
provides the flexibility of mixed compiled and interpreted
simulation and an efficient incremental compilation.

Fintronic has a mission to supply the highest performance
Verilog HDL simulators available for full language design
verification and timing simulation. It is privately held and
privately funded.



Super FinSim v9.1.12 LINUX64 英文正式版(附帶OVI的Virology編譯器軟體)

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